Successive approximation circuits are often used to implement analog-to-digital converters (ADCs). FIG. 1 shows a prior art successive approximation ADC circuit 100. As observed in FIG. 1, the successive approximation ADC includes a sample-and-hold circuit 101 to receive an analog input signal. The sample-and-hold circuit samples the analog input signal when a next analog-to-digital conversion operation is to begin and “holds” this signal at the sampled value throughout the conversion. In the case where the analog input signal is a voltage, sample and hold circuit 101 may be implemented, e.g., with a capacitor in series with a switch. The switch can be normally closed and when an analog-to-digital conversion operation is to begin, the switch is opened holding the input voltage on the capacitor.
The held analog signal is fed to a comparator circuit 102 which serves to generate a difference signal (or error term) for a feedback loop that includes a successive approximation logic block 103, a successive approximation register 104 and a digital to analog (DAC) converter 105. As will be explained in more detail immediately below, an analog-to-digital conversion operation is performed by recursively performing a number of successive approximations through the feedback loop.
For the initial recursion of an analog-to-digital conversion operation, the successive approximation logic block 103 provides a digital value to its successive approximation register 104 that is approximately halfway between the numeric range of the register's digital output bit width. Other implementations of the successive approximation may choose to start at another value such as a maximum value, a minimum value, a last value or any other value. For simplicity the remainder of the instant docket will refer to an implementation in which the successive approximation approach starts at a halfway value.
The “halfway” value is typically implemented by setting the highest ordered bit in the successive approximation register 104 “high” while keeping each of the remaining lower ordered bits “low”. For example, if the successive approximation register 104 has an eight bit output, its numeric output range is 256 (2^8=256). Setting the highest ordered bit high corresponds to a “halfway” value of 128 (10000000). Each successive approximation recursion ends with a new value being presented in the successive approximation register 104. Thus, at this point, the first recursion for the analog-to-digital conversion operation is completed.
The halfway value from the successive approximation register 104 is then converted by the DAC 105 to an analog signal that is nominally situated halfway within the designed-for input dynamic range of the ADC circuit 100. The input signal being held by the sample and hold circuit 101 is then compared against the signal generated by the DAC 105. The output signal from the comparator 102 in response to the comparison begins the next recursion of the analog to digital conversion operation.
If the signal from the DAC 105 is less than the held input signal from the sample and hold circuit 101, the comparator 102 sends an increment (“up”) signal to the successive approximation logic 103. In response to an increment signal, the successive approximation logic 103 keeps the higher ordered bit(s) from the previous recursion(s) in the digital output signal of the successive approximation register 104 and sets the next highest ordered bit to be “high” (e.g., in the case where the first recursion output was 10000000, the second recursion output would be 11000000).
By contrast, if the signal from the DAC 105 is larger than the held input signal from the sample and hold circuit 101, the comparator 102 sends a decrement (“down”) signal to the successive approximation logic 103. In response to the decrement signal, the successive approximation logic 103 decrements the value of the higher ordered bit(s) from the previous recursion(s) in the digital output signal of the successive approximation register 104 and sets the next highest ordered bit to be “high” (e.g., in the case where the first recursion output was 10000000, the second recursion output would be 01000000 or 0111111).
As can be appreciated, according to this operation the digital output of the successive approximation register 104 will approach the value of the input signal with each next recursion and will eventually reach a steady state when the difference between the output of the DAC 105 and the input signal is equal to or less than the output resolution of the DAC 105. At this point, the value of the successive approximation register is latched into an output register 106 so that the formal output of the ADC can be provided.